In modern digital systems, serial data are transferred between various elements of the system. It is recognized that others have done work in various systems. They have devised multi-mode digital enciphering systems which may be utilized on full duplex and half duplex communication channels as illustrated by U.S. Pat. No. 4,169,212 to Federick A. Kinch, Jr. et al, issued Sep. 25, 1985. Unlike the present application others have developed processor to peripheral interfaces for asynchronous or synchronous applications dealing with parallel data transmission, as illustrated by U.S. Pat. No. 4,785,469, to Sunil Joshi et al, issued Nov. 15, 1988. Variable rate data has been recovered by very complex methods based on patent recognition, as illustrated by U.S. Pat. No. 4,087,681 to John P. Spencer et al, issued May 2, 1978. Similarly complex is U.S. Pat. No. 4,756,010 to Leonard E. Nelson, issued Jul. 5, 1988 wherein a method of recovery was proposed that was intended to work for slower transmission rates where the receiving data contains a clock that is many time faster than the data transmission clock.
When the transmitter and receiver contain clocks which are asynchronous to each other, it becomes necessary for the receiving device to become synchronized with each incoming serial data in order to receive the data correctly. To accomplish this, the receiving device must generate a clock in synchronization with the incoming data and in turn use that clock to receive the data.
As will be seen from what we have developed, for very high transmission rates it is not desirable to have a clock which is many times faster than the transmission rate, and there is similarly needed a system which works for a fixed data rate without any need for pattern recognition. The present application relates to serial data transmission and recovers a clock for clocking the serial data. In this case, others have selected from an N phase-shifted clock that is in sync with incoming data for determining a bit clock in a data receiver from a first bit sequence of alternating half-bits received from a data transmitter after generating a local clock signal and generating a plurality of phase shifted local clock signals of equal frequency from the local clock signal, see U.S. Pat. No. 4,817,117 to Manfred Tasto et al. issued Mar. 28, 1989. This proposal did not become widely used and required generating a bit clock signal from at least one of the phase shifted local clock output signals during a predetermined minimum time interval. The system was intended to be applicable to cordless telephone sets, and required strings of bits to be generated (about 16 bits per string) to synchronize and recognize a pattern. It had need for complex hardware to do the job required.
A widely used serial data recovery scheme is based on phase-locked loop (PLL) oscillators, which entails sending serial data as a message with preamble which allows the PLL to get synchronized to the incoming serial data. In addition, the data message is encoded into special codes, such as 8 BIT/10 BIT codes, which guarantee incoming data transitions every several bits; this is used to continuously calibrate the PLL for the duration of the message, so that it remains in synchronization with the incoming data. These methods have been proven to work very well, especially for long messages. Long messages permit the overhead associated with the preamble and PLL continuous calibration to be amortized over a long period of time, such that its effect becomes negligible or small.
However, with the advent of parallel processing there has arisen a need for lower latency serial data recovery methods capable of handling short messages efficiently with a very small overhead. The conventional methods will NOT work for low-latency requirements, because the time required to synchronize a PLL oscillator via the preamble is much longer than the time to transmit a small amount of data. Such an approach would be very detrimental to performance.
In addition, there is a need in systems utilizing interconnection networks and many different clock sources to change synchronization quickly. For instance, the recovery method must synchronize quickly to receive a first message, then must be capable of resynchronizing very quickly to a different asynchronous source in order to receive a second message immediately.
Whenever data is recovered asynchronously, the possibility of circuit instability, referred to as metastability, exists and must be taken into account, as we have done with the present apparatus.
In summary, for future applications we have recognized a need for a faster and cheaper, more flexible and less complex approach to serial fixed data rate transmissions of very high rates.